This invention related to a multilevel interconnection structure useful particularly In semiconductor integrated circuits and a method of producing the multilevel interconnection structure.
In recent semiconductor integrated circuits, multilevel interconnections are widely used.
A conventional two-level interconnection structure is shown in FIG. 5. An insulating layer 52 is formed on a surface of a silicon substrate 50, and first-level interconnecting lines 54 are laid on the insulating layer 52. The interconnecting lines 54 are formed by first forming a total layer, usually an aluminum layer, on the insulating layer 52 and then patterning the metal layer by photolithography using a photoresist and subsequent etching. The interconnecting lines 54 are buried in a silicon oxide film 56 which is deposited on the insulating layer 52 after forming the interconnecting connecting lines 54. So, the spacings between the interconnecting lines 54 are filled with the deposited silicon oxide 56. The silicon oxide film 56 serves as an interlayer insulator. In the silicon oxide film 56 contact holes 58 are formed above some of the interconnecting lines 54 which are to be connected with interconnecting lines on the upper level, and the contact holes 58 are filled with a metal such an tungsten to provide interlayer connection plugs 60. After that, second-level interconnecting lines 62 are laid on the silicon oxide film 56 by patterning a metal layer.
With the progress of miniaturization of semiconductor devices and enhancement of the operation speed of the devices, multilevel interconnection structures are required to reduce capacitance between interconnections on upper and lower levels and also capacitance between adjacent interconnecting lines on each level. Capacitance between interconnections on upper and lower levels can be reduced by using a low permittivity insulator as the material of the interlayer insulating film and by increasing the thickness of the interlayer insulating film, and this is practicable. Capacitance between adjacent interconnecting lines on each level reduces if the spacings between the lines are widened, but this is contradictory to the desire of enlarging the scale of integration by narrowing the line space.
For the purpose of reducing the capacitance between adjacent interconnecting lines, JP-A 5-35841 proposes a multilevel interconnection structure in which a cavity is formed around and along an interconnecting line in order to utilize low permittivity of air. FIGS. 6(A) to 6(D) illustrates a process of producing the proposed structure.
Referring to FIG. 6(A), in insulating layer 72 is formed on a silicon substrate 70, and interconnecting lines 74A, 74B are laid on the insulating layer 72 by patterning a metal layer. The interconnecting line 74A is to be connected with interconnections on the upper level, and the line 74B does not need to be connected with interconnections on the upper level. A silicon nitride film 76 is deposited on the insulating layer 72 so as to completely bury the interconnecting lines 74A, 74B in the dielectric film 76, end a silicon oxide film 78 is deposited on the silicon nitride film 76. Above the interconnecting line 74A, a hole 80 is formed in the silicon oxide film 78. Referring to FIG. 6(B), a photoresist layer 82 is formed on the silicon oxide film 78, and in an elongate region above the interconnecting line 74B a number of small holes 84 are formed through the photoresist layer 82 and the oxide film 78 by photolithography and subsequent etching. Using the holes 84, the silicon nitride film 76 in a region above and alongside the interconnecting line 74B to removed by dry etching in order to form a cavity 86 around and along the interconnecting line 74B. Referring to FIG. 6(C), the photoresist layer 82 is removed, and a spin-on-glass is applied to the exposed surface of the silicon oxide film 78 and sintered to form a dielectric layer 88. At the position of the aforementioned hole 80 above the interconnecting line 74A, a contact hole 90 is formed through the insulating layers 88, 78 and 76, and the hole 90 is filled with a metal to provide an interlayer connection plug 92. An shown in FIG. 6(D), second-level interconnection lines 94 are formed on the dielectric layer 90 by patterning a metal layer.
In the structure shown in FIG. 6(D), the cavity 86 serves the purpose of reducing the capacitance between the interconnecting line 74B and the adjacent interconnecting line 74A. However, the cost of interconnection increases since complicated process steps are needed to form the cavity 86. Besides, when the spacing between the interconnection lines 74A and 74B is very narrow this method is impracticable because the cavity 86 for the line 74B and the contact hole 90 for the line 74A may connect with each other. Furthermore, capacitance between adjacent interconnecting lines in reduced only in limited regions of the interconnection structure since the cavity cannot be formed around interconnecting lines which are connected to interconnections on the upper or lower level.